1. Field of the Invention
The present invention pertains to the field of semiconductor transistors. More particularly, this invention pertains to the field of reducing capacitance in transistors with electrostatic discharge protection structures.
2. Background of the Related Art
In an effort to improve performance in computer systems, bus interfaces between computer system components are being pushed to higher and higher switching rates. A limiting factor in increasing bus switching rates is the capacitance of the signal pins of components that are connected to the bus. The capacitance of the signal pins reduces the switching frequency that can be obtained while maintaining proper signal integrity. The pin capacitance is made up of several factors such as package leadframe capacitance, bondpad capacitance, electro-static discharge (ESD) protection structures, and output driver (transistor) capacitance.
FIG. 1 shows an example of a transistor with ESD protection. The transistor 100 of FIG. 1 includes a source region 140 formed in a substrate 110, a source contact 145, a gate 130 formed on a dielectric material 135, a drain region 120 formed in the substrate 110, and a drain contact 125. The drain region 120 is made large in order to prevent current crowding. Current crowding during an ESD event may cause a large current to focus on a small area of semiconductor material and thus cause damage to the device. By increasing the size of the drain region, the current during an ESD event is less likely to focus on a small area, thereby reducing the likelihood of damage to the device.
The increased size of the drain region as described above has the disadvantage of increasing the output drain capacitance, perhaps by as much as 2 or 3 times over minimum dimensions. The output drain capacitance is largely a function of drain region area and depletion region width at the p-n junction formed by the substrate 110 and the drain region 120.
FIG. 2 depicts a transistor 200 embodying a technique used to reduce the output drain capacitance while maintaining ESD protection properties. The transistor 200 includes a source region 240 formed in a substrate 210, a source contact 245, a gate 230 formed over a dielectric material 235, a first drain region 230 formed in the substrate 210, a resistive region 215 formed in the substrate 210, a second drain region 227 formed in the substrate 210, and a drain contact 225 formed on the second drain region 227. In transistor 200, the resistive region 215 provides the ESD protection. The resistive region 215 is of the same conductivity type as the first and second drain regions 220 and 227, but is more lightly doped. Because the resistive region 215 is lightly doped, the depletion region width at the p-n junction formed by the substrate 210 and the resistive region 215 is much greater that the depletion region width achieved by the transistor 100 of FIG. 1. The increase in depletion region width results in a decrease in capacitance while maintaining ESD protection characteristics.
The above mentioned transistors 100 and 200 require different steps during the fabrication process. The formation of the transistor 200 requires that the resistive region 215 be formed then a mask to be formed over the resistive region 215 during the formation of the source region 240 and drain regions 220 and 227. Many processes that fabricate transistor structures similar to that of the transistor 100 depicted in FIG. 1 typically do not readily the ability to form the structure shown in FIG. 2 due to the extra steps involved in masking the resistive region during formation of the source and drain regions. Consequently, while some processes are able to take advantage of the capacitance reduction using the structure shown in FIG. 2, many are not. For these reasons, a reduced-capacitance transistor with ESD protection that can be fabricated without significant additional processing is desirable.